Challenges for on - Chip Interconnection Networks

......VLSI technology’s increased capability is yielding a more powerful, more capable, and more flexible computing system on single processor die. The microprocessor industry is moving from singlecore to multicore and eventually to manycore architectures, containing tens to hundreds of identical cores arranged as chip multiprocessors (CMPs). Another equally important direction is toward systems on a chip (SoCs), composed of many types of processors on a single chip. Microprocessor vendors are also pursuing mixed approaches that combine multiple identical cores with different cores, such as the AMD Fusion processors combining multiple CPU cores and a graphics core. Whether homogeneous, heterogeneous, or hybrid, cores must be connected in a high-performance, flexible, scalable, design-friendly manner. The emerging technology that targets such connections is called an on-chip interconnection network (OCIN), also known as a network on chip (NoC), whose philosophy has been summarized as ‘‘route packets, not wires.’’ Connecting components through an onchip network has several advantages over dedicated wiring, potentially delivering high-bandwidth, low-latency, low-power communication over a flexible, modular medium. OCINs combine performance with design modularity, allowing the integration of many design elements on a single die. Although the benefits of OCINs are substantial, reaching their full potential presents numerous research challenges. In 2006, the National Science Foundation initiated a workshop to identify these challenges and to chart a course to solve them. The conclusions we present here are the work of all the attendees of the workshop, held last December at Stanford University. All the presentation slides, posters, and videos of the workshop talks are available online at http://www.ece.ucdavis. edu/,ocin06/program.html. John D. Owens